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Disassembler and Analyser of Binary Code
Bayer, David ; Smrčka, Aleš (referee) ; Peringer, Petr (advisor)
This thesis is focused on binary code disassembly. It describes the design of ARM and AVR architectures and does a research into existing solutions. Based on this knowledge, we designed and implemented a disassembler-like application. The application provides a graphical user interface to facilitate the starting of disassembly and displays the result. The designed environment is extensible to more disassemblers, disassembly algorithms, and code analysis.
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Emulator of Simple Processor
Kuzník, Petr ; Přikryl, Zdeněk (referee) ; Křoustek, Jakub (advisor)
Emulator will be designed as generic emulator. It should be capable of emulating versatile architectures. Each architecture will be stored in separate module implemented as dynamically linked dll libraries. Main goal is for the emulator to be generic and design its structure in a way, so that it would be possible to easily add new architecture modules and design these modules with already implemented abstractions. Primarily implemented architecture will be Commodore 64. It is a personal computer used mainly in USA during 1980s.
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Implementation of General Assembler
Husár, Adam ; Masařík, Karel (referee) ; Hruška, Tomáš (advisor)
This thesis describes the design of the universal assembler that represents a part of the Lissom project. You will be provided with the description of the assembler architectures and their usual tasks. Special attention is paid to GNU assembler. Designed assembler consists of the fixed and the generated part. The generated part is created automatically from the description of instruction set, that is defined using architecture and instructions set description language ISAC. Using this approach, it is possible to change assembler target architecture automatically. The second part of thesis describes the Parserlib2 library implementation that is a part of the Lissom project and provides the information about the target instruction set for an assembler generator.
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A CPU Emulator for Course of Assembly Languages
Charvát, Lukáš ; Samek, Jan (referee) ; Smrčka, Aleš (advisor)
The master thesis discusses the design of an emulator of a CPU architecture instruction set aimed at assembly languages course. While most of nowadays emulators are architecture specific, the emulator proposed in master thesis aims at education and better understanding of assembly languages. The emulator is not limited to a single CPU, but it easily allows defining a purpose-specific architecture and instruction set in order to perform operations upon it and to display its current state.
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Interactive Disassembler
Mrva, Milan ; Přikryl, Zdeněk (referee) ; Křoustek, Jakub (advisor)
This thesis describes procedures and tools of reverse engineering in terms of software development. There are introduces different techniques of protection against decomposition of executables. The work also mentions some programs used for decomposition analysis. Furthermore it contains information about architecture of processing units, with emphasis on microprocessors Intel and Motorola. Variety of executable formats is shown. Generic retargetable disassembler was implemented. There is a description of its structure and plugins. These plugins represents three algorithms used for disassembling a program. One of them applies a multi-process parsing engine, which is an own design by author of the thesis. At the end, these techniques are compared and further development is outlined.
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NIOS II Processor Model
Masařík, Marek ; Dolíhal, Luděk (referee) ; Zachariášová, Marcela (advisor)
This bachelor thesis deals with the implementations of Nios II processor model in the description language processor called description CodAL. The implementation of processor is on two levels of abstraction. First level of abstraction is the instruction accurate model and second is the cycle accurate model. An important part of processor design is testing and verification which were realized on the prepared benchmark set. The resulting processor can be potentially used in real applications.
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Modelling of PowerPC Processor
Blaha, Hynek ; Dolíhal, Luděk (referee) ; Masařík, Karel (advisor)
Processor architectures are becoming increasingly complex, so great emphasis is put on the automation of their desings. This bachelor thesis describes the design of the PowerPC processor architecture in Codal language. The model is created according to avaliable documentation. The functionality and efficiency of the model was verified by tests provided by research group Lissom and compared to current competitor.
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Development and Testing Support for Interpreters of Simple Languages
Mazancová, Lenka ; Láznička, Stanislav (referee) ; Křivka, Zbyněk (advisor)
This document is focused on analysis, design and implementation of a reference interpreter that can be used as a tool for fulfilling and evaluating the team project of Formal Languages and Compiler course. The solution of this task includes the design a new instruction set, a library for reading and writing for this instruction set and an interpreter of this instruction set. Special attention is payed to the interpreter itself that can be extended to accept modifed instruction set. Such extension is described using XML configuration files and extern source files in C# or Visual Basic.NET. In the end the text describes the testing of the interpreter of the design instruction set including the possibilities to adjust the instruction set to different types of high-level languages.
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Disassembler and Analyser of Binary Code
Bayer, David ; Smrčka, Aleš (referee) ; Peringer, Petr (advisor)
This thesis is focused on binary code disassembly. It describes the design of ARM and AVR architectures and does a research into existing solutions. Based on this knowledge, we designed and implemented a disassembler-like application. The application provides a graphical user interface to facilitate the starting of disassembly and displays the result. The designed environment is extensible to more disassemblers, disassembly algorithms, and code analysis.
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